Measurement Algorithm of Clock Jitter Based on Sequential Equivalent Sampling

For the problem that general characteristic impedance measurement instrument is difficult to measure the size of clock jitter, this paper proposes a measurement algorithm to achieve clock jitter based on sequential equivalent sampling. First, according to the relationship between the equivalent sampling signal and the average signal, we count up the probability density distribution of the clock jitter and use the Tailfit jitter separation techniques to decompose total jitter (TJ) into deterministic jitter (DJ) and random jitter (RJ), then count up the peak-to-peak values of periodic jitter (PJ), cycle-to-cycle jitter (CCJ) and time interval error (TIE) to achieve a precise measurement of clock jitter. Finally we use the test results of jitter analysis software of Tektronix’s TDSJIT3 as a reference to verify the effectiveness of the algorithm. This algorithm provides quantitative analysis means for the stability of characteristic impedance measurement instrument, and provides the reference basis for self-calibration circuit design of subsequent hardware.